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Serge93's avatar
Serge93
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Agilex™ 7 FPGA I-Series Development Kit - Only one PCIe RP Gen4x4 on the R-Tile

Hello, I would like to use only one Root Port PCIe Gen4x4 on the R-Tile of an Agilex 7 I-Series. When I create the PCIe IP, four PCIe IP of Gen4x4 are created. What should be done to disable the t...
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VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
1 year ago

Hi Serge,


Thanks, you have a great day as well!


I’m glad that your question has been addressed. I now transition this thread to community support. If you have a new question, please login to https://supporttickets.intel.com/, view details of the desire request, and post a feed or response within the next 15 days to allow me to continue to support you. After 15 days, this thread will transition to community support. The community users will be able to help you with your follow-up questions.


Best Regards,

Ven