Forum Discussion
6 Replies
- Altera_Forum
Honored Contributor
Does conf_done go high for a while (some µs) or is it always down at the end of the programming?
Maybe your board has not enough power to drive the design in the FPGA? Look at the core voltage (1.2V) and vccd_pll voltage. Is there a fall at the end of the programming? Maybe it isn't a voltage issue but I had once a similar problem... - Altera_Forum
Honored Contributor
COF_DOEN is always low!
- Altera_Forum
Honored Contributor
And the power is 1.2 and 3.3 after programming!
There is no fall at the end of the programming! - Altera_Forum
Honored Contributor
OK! It works!
- Altera_Forum
Honored Contributor
what was the problem?
- Altera_Forum
Honored Contributor
nCS did not pull down!