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Altera_Forum
Honored Contributor
Honored ContributorAES-128 Sbox - Rom Issue
Hello, I am a student and for my final year project am carrying out an investigation into the hardware implementation of AES-128 in an Altera FPGA - using SystemVerilog. In the AES algorit...
Altera_ForumHonored Contributor
Honored ContributorYou need to be able to generate the ROM's read address in the clock cycle before you need the data.
I was looking at your code snipped and it looked possible. But I may be wrong here.
