Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorAES-128 Sbox - Rom Issue
Hello, I am a student and for my final year project am carrying out an investigation into the hardware implementation of AES-128 in an Altera FPGA - using SystemVerilog. In the AES algorit...
Altera_ForumHonored Contributor
Honored ContributorGreat reply- thanks!
However, even if I was to use 4 x ROM (or 2 x Dual Port), I don't understand how there can be no performance penalty? As you still need to wait a full clock cycle to get a result?
