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Altera_Forum
Honored Contributor
Honored ContributorAES-128 Sbox - Rom Issue
Hello, I am a student and for my final year project am carrying out an investigation into the hardware implementation of AES-128 in an Altera FPGA - using SystemVerilog. In the AES algorit...
Altera_ForumHonored Contributor
Honored ContributorThank you both for your replies - very much appreciated.
My main issue with using a Synchronous ROM is as follows... My design uses a FSM, having 13 states - and on each clock cycle the state is increased (generally speaking, in each state, 1 round of encryption/decryption is performed). When using an array, thus the LUT's the instruction... for (shortint c = 0; c < 4; c++) begin State[r][c] = Sbox[State[r][c] >> 4][State[r][c] & 8'h0f]; end Would carry out all 4 substitutions within a single clock cycle, however by using a ROM that piece itself would take 4 clock cycles. How would I synchronise my current FSM using a ROM - would I have to increment states every X clock cycles instead of every 1?
