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Altera_Forum
Honored Contributor
Honored ContributorAES-128 Sbox - Rom Issue
Hello, I am a student and for my final year project am carrying out an investigation into the hardware implementation of AES-128 in an Altera FPGA - using SystemVerilog. In the AES algorit...
Altera_ForumHonored Contributor
Honored ContributorThe M*K blocks in Altera's FPGAs can only implement synchronous RAM/ROMs. Ie, they have the 1 cycle delay.
Asynchronous ROMs need to be implemented in LUTs.
