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Altera_Forum
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14 years ago

AES-128 Sbox - Rom Issue

Hello, I am a student and for my final year project am carrying out an investigation into the hardware implementation of AES-128 in an Altera FPGA - using SystemVerilog. In the AES algorit...
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Altera_Forum
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14 years ago

You can refer Altera's cookbook. I dont think you can infer asynchronous ROM. I don't understand the meaning of "slow design". If you mean latency, proper pipelining will decrease the overall latency rather than increasing it.