Advice on FPGA pin choice for a kit.

Question

I am designing a kit vor academic use here at my university. I am using an EP4C6 device with 144 EQFP package. For some reasons, not importanting mentioning here, i wont be able to leave all pins routed to expansion headers or peripherals. So i have a choice to make. The board got a 50Mhz oscillator connected to a dedicated clock pin. I already routed a differential clock pair (connected in the oposite side to make use of the other PLL) to the expansion header. And now i must chose betwen an extra dedicated clock pin (close to the 50Mhz oscillator) and a standard IO. What do you guys say? How ofter do you think a student would need more than an extra pair of dedicated clock pins? I know that would be related to the application, but as this is a veri generic basic kit there is none.

Best regards,

LR

altera_forum · Answer

Will you have at least one header for I/O?

I would recommend making a clock pin available from an external source. The dedicated clock pins are input-only. If you want to make the external pin useable as both a clock or a user I/O, then you could tie two pins together, i.e., route the signal from the header pin to both a dedicated clock input and to an I/O pin. This will increase the capacitance of the signal, but since you're running the signal to a header, you've already got an ugly transmission line, so its not really going to be that bad.

I mention this idea because of an issue I recently noticed. The Arrow BeMicro USB board does not route any clocks to its 80-pin expansion header, so you cannot use an external device that uses an external clock, eg., an ADC or DAC. The Arrow BeMicro-SDK does have clock pins on its edge connector. However, since those pins are input only, so they are not as 'general purpose' - I like the idea of routing a header signal to two pins to get the best of both worlds :)

How much do you think you kit will cost? Its pretty hard to beat the price of Terasic's DE0-nano ...

Cheers,

Dave

altera_forum · Answer

Hello,

Thank your for your sugestions. The board got a total of 54 expansion pins, already incluiding the differential clock pair and this specific header i am talking about. It is not a super critical as there are already 2 dedicated input clocks and 51 IOs... but i like to ask people due to experience with other kits, as yours with BeMicro. Taking that in consideration, what would be your advice? Clock or IO (or both???)

The board will be cheaper than DE0-Nano, but with a much smaller FPGA (no free lunch here). In a general perspective the users that we are targeting with this board are more general purpose hobists that are willing like to take a try with FPGA. When i say academic purposes are for are not strictly academic enviroment. For very local reasons, FPGA is almost non existent outside of professional hardware desing market. I live in Brazil and our taxes are 100% over electronic devices. So for a non-academic user the Altera DE0-Nano costs about 150 USD + 40USD of Shipping Costs + about 22 USD of custom clearance services, what starts to be a bit expensive for someone that is just thinking on taking a try on FPGAs.

Best regards,

LR

altera_forum · Answer

--- Quote Start ---

Thank your for your sugestions. The board got a total of 54 expansion pins, already incluiding the differential clock pair and this specific header i am talking about. It is not a super critical as there are already 2 dedicated input clocks and 51 IOs... but i like to ask people due to experience with other kits, as yours with BeMicro. Taking that in consideration, what would be your advice? Clock or IO (or both???)

--- Quote End ---

What you have proposed sounds sufficient.

--- Quote Start ---

The board will be cheaper than DE0-Nano, but with a much smaller FPGA (no free lunch here). In a general perspective the users that we are targeting with this board are more general purpose hobists that are willing like to take a try with FPGA. When i say academic purposes are for are not strictly academic enviroment. For very local reasons, FPGA is almost non existent outside of professional hardware desing market. I live in Brazil and our taxes are 100% over electronic devices. So for a non-academic user the Altera DE0-Nano costs about 150 USD + 40USD of Shipping Costs + about 22 USD of custom clearance services, what starts to be a bit expensive for someone that is just thinking on taking a try on FPGAs.

--- Quote End ---

Good, it sounds like you have done your "Market Research" :)

One other thing you might want to consider is packaging. The DE0-nano and boards like it cannot be placed in an enclosure easily. If you think people will be interested in using these boards for control systems or "black boxes" for controlling motors etc, see if you can create a board form-factor that allows an enclosure to be used, but still allows access to the connectors. This is not a critical requirement, just an observation ...

Make sure to think about ESD protection and voltage protection on the I/Os going off the board.

Cheers,

Dave

altera_forum · Answer

Hello Dave,

Thank you for your recomendations. But regarding the original question, i could not understand your final opinion. Considering that there are already 2 dedicated clock pins and 51 IOs, what do you recomend to do with the remaining pin? Clock or IO?

In general, when you (or whoever is reading this) is using a generic kit, what usually would be a good relation of IOs and Clock pins.

Best regards.

altera_forum · Answer

--- Quote Start ---

But regarding the original question, i could not understand your final opinion. Considering that there are already 2 dedicated clock pins and 51 IOs, what do you recomend to do with the remaining pin? Clock or IO?

--- Quote End ---

An I/O pin.

However, resistors are essentially free (and so are empty PCB pads), so you could also route the last header pin via a resistor to both an I/O and the clock input pin. Load the I/O resistor by default.

--- Quote Start ---

In general, when you (or whoever is reading this) is using a generic kit, what usually would be a good relation of IOs and Clock pins.

--- Quote End ---

A clock pin per I/O connector is fine.

If I want to test an ADC or DAC or some other device that needs a clock, then I would generally only want to test one of them, so one clock per I/O header is sufficient.

More suggestions:

1) does the FPGA have PLL_OUT pins? Make sure you route some of them to the header. That way your users have the option of generating a clock at the FPGA and routing it to external logic.

2) power to the header

If you have 3.3V on the header for powering external logic, add a jumper or a FET to control whether that power is on or off. Quite often I like to connect kits and if both kits have a power pin, this makes connecting them directly with a cable difficult - the power wire in the cable needs to be cut.

Cheers,

Dave

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Advice on FPGA pin choice for a kit.

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