--- Quote Start ---
But regarding the original question, i could not understand your final opinion. Considering that there are already 2 dedicated clock pins and 51 IOs, what do you recomend to do with the remaining pin? Clock or IO?
--- Quote End ---
An I/O pin.
However, resistors are essentially free (and so are empty PCB pads), so you could also route the last header pin via a resistor to both an I/O and the clock input pin. Load the I/O resistor by default.
--- Quote Start ---
In general, when you (or whoever is reading this) is using a generic kit, what usually would be a good relation of IOs and Clock pins.
--- Quote End ---
A clock pin per I/O connector is fine.
If I want to test an ADC or DAC or some other device that needs a clock, then I would generally only want to test one of them, so one clock per I/O header is sufficient.
More suggestions:
1) does the FPGA have PLL_OUT pins? Make sure you route some of them to the header. That way your users have the option of generating a clock at the FPGA and routing it to external logic.
2) power to the header
If you have 3.3V on the header for powering external logic, add a jumper or a FET to control whether that power is on or off. Quite often I like to connect kits and if both kits have a power pin, this makes connecting them directly with a cable difficult - the power wire in the cable needs to be cut.
Cheers,
Dave
Honored Contributor
