Occasional ContributorWe have two dimms of same capacity. I know number of bits for row, column, bank and bank group and it is byte addressable. For a burst length of N, how can I figure out address mapping for this ?
Regular ContributorHello,
Address ordering [26 bits]
Row 16, Column 10, Bank 2, Bank Group 2. Address Ordering is CS-CID-Row-Bank-Col-BG.
The Avalon bus address width is 27 bits shown as amm_address[26..0] in the IP Block Symbol view or in the RTL top level file port description.
The mapping is :
Row[15..0] = amm_address[26:11]
Bank[1..0] = amm_address[10:9]
Col[9..3] = amm_address[8:2]
Bank Group[1..0] = amm_address[1:0]
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