address decoding in vhdl

You can use the higher address bus lines.

Example: If you use the a12 and a13 lines

cs=a12 and a13;

cs is the chip select signal for uart. In this case the base address is 0x3000

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hello,

but to do the address decoding in vhdl, i dont have any idea how to write it..can someone guide me on how to do this ??

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It is very simple to write the VHDL code for an address decoder. A general code can be as follows:

2-to-4 address decoder: Using if-else construct

====================

if address = "00" then

selection_lines <= "0001";

elsif address = "01" then

selection_lines <= "0010";

elsif address = "10" then

selection_lines <= "0100";

else address = "11" then

selection_lines <= "1000";

end if;

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You can also use "case-select" and "when-else" constructs to code an address decoder.

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which one is the address for the uart? 00 or 01 0r 10 or 11? should i fix the address of uart in my uart module?

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"00", "01" are the addresses which you will be decoding. The "0001", "0010" etc. are the output selection lines of the decoder.

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"00", "01" are the addresses which you will be decoding. The "0001", "0010" etc. are the output selection lines of the decoder.

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i still understand what you meant. the data output of my soft-core processor is 32 bits width. this data output will be passed to the input of uart. do i need address choices when only uart is connected to the processor and no other??

hello,

in my attachment is my zpu_core(my processor) and a uart. mem_write is data output from my processor.it has 32 bits width.how to write an address decoder between zpu_core and uart serial?? i'm still thinking about it...any starting idea would be greatly appreciated..

Thx

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"00", "01" are the addresses which you will be decoding. The "0001", "0010" etc. are the output selection lines of the decoder.

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hello vizzie,

are selection lines the output data? and "00", "01" for example as addresses for the selection_lines??

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hello vizzie,

are selection lines the output data? and "00", "01" for example as addresses for the selection_lines??

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That's right. Selection lines is the output of the decoder. "00", "01" are the addresses from the hypothetical source; in this case your zpu processor.

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hello,

in my attachment is my zpu_core(my processor) and a uart. mem_write is data output from my processor.it has 32 bits width.how to write an address decoder between zpu_core and uart serial?? i'm still thinking about it...any starting idea would be greatly appreciated..

Thx

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I saw your attachment. However all the signals for the uart can not be seen in the snapshot (please post it again). A rough idea is as follows:

1. You need to decode the address to select the uart component. This means when the address lines of the processor are loaded with values pertaining to the address space of the uart, there has to be some means to start the uart operation.

2. I don't see any address lines in the uart component. Does it have a select/enable component? In that case when the uart address is loaded on the zpu address bus, the select/enable lines should go high for the uart. You need to write an if-else type of construct for this. This is what we would call address decoding in this case.

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hello vizzie,

see my attachments(uart and zpu in vhdl and bdf files). thx

regards,

bruno

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I saw your files and have following suggestions:

1.Write logic to decode the out_mem_addr, out_mem_writeEnable and out_mem_readEnable to control tx_data_en, rx_data_en and rest of the uart. For example:

==================

if out_mem_addr = "uart_address" then --where uart-address is pre-defined

if out_mem_writeEnable = '1' then

tx_data_en <= '1';

tx_data_in <= relavant data;

else

tx_data_en <= '0';

tx_data_in <= (others => '0');

end if;

--Similarly decode out_mem_readEnable with rx_data_en and rx_data_out etc.

else

--do nothing or reset the uart.

end if;

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2. This would be one way to decode the address of uart.