address decoding in vhdl

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where should i define my uart address?? in my uart_serial.vhd??

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You don't need to define uart_address. A uart doesn't need an address, right? The addresses are from the processor. A peripheral to a processor needs an address.

So we have double whammy here :). Question: There are address lines coming from a processor but our peripheral/device has no port which looks like an address line. What do we do? Answer: Use some enable signal like chip_select or tx_enable which kicks off the peripheral to work as an equivalent to an address line.

there is blockram instantiated in my zpu_core.vhd. does this decoder take out one by one the data in the blockram(in attachment)?? can you give me examples of chip_select?? out_mem_addr(14 downto 0)="00000000000000", then

chip_select='1'?? am i right??

thx

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there is blockram instantiated in my zpu_core.vhd. does this decoder take out one by one the data in the blockram(in attachment)??

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I can't say. You will have to simulate the design and verify. The decoder is meant to decode the addresses of the processor not that of a memory. A good reading of processor basics should clear your doubts: http://en.wikipedia.org/wiki/microprocessor

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can you give me examples of chip_select??

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Some good examples can be the select lines of a mux, enable lines of a counter and CS signals of external memories.

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out_mem_addr(14 downto 0)="00000000000000", then

chip_select='1'?? am i right??

thx

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No. The address should be that of a processor.

hello vizzie,

i just realized that rs232 cant handle 31 bits. mem_write is 32 bits width. that means what comes out of my address decoder is also 32 bits width. tx_data_in must not be more than 8 bits..do you have any idea on this?

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hello vizzie,

i just realized that rs232 cant handle 31 bits. mem_write is 32 bits width. that means what comes out of my address decoder is also 32 bits width. tx_data_in must not be more than 8 bits..do you have any idea on this?

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I suppose you mean you have 32 bits data bus from the processor and the device data width is only 8-bits (right?). If there are no specific bus-arbitration rules in zpu (which appears to be true), then what abt connecting the least significant 8-bits of data-bus to tx_data_in?

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that means, if i only use the 8 least significants bit, will i have the same output data as before??

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Yes I believe so, though you must check this out.