Forum Discussion
Altera_Forum
Honored Contributor
8 years agoWell, seems I found my problem. I was definitely failing timing. I'm still working out timing in the whole design, but the 64KB of on-chip memory added many cycles worth of slack for some reason; all default tests failed. I reduced to 5KB, and I am now off time by 5ns. The design at least loads, but I need to add a few pipelines in my design.
For anyone else who has this problem, ensure you meet timing!!