adding information regarding expected timing in the LPM_ADD_SUB section of the user guide

To help an engineer make an informed decision about using any of the integer arithmetic IP cores, it would help immensely if some timing information was provides in the user's manual.

taking as an example the LPM_ADD_SUB IP core (page 22 in the manual)

some indication for the expected timing:

- when no pipelining is deifned, what is the expected input-to-output propagation delay for such an IP core? Dependencies on core parameters, target FPGA family, speed grade, etc exist, of course, but some examples for specific families and speed grades would be helpful: for example 8-bit/16-bit/32-bit adder-only in a Cyclone V, speed grade x, etc.

- when pipelining is defined, what is the expected clock frequency that the IP core could operate at? (for dependencies, same as above).

It is understood that such timing information, if available, could only serve as a rough guide to the designer, but they would still be very useful in making a choice between pipelining/non-pipelining and, if pipelined, how many pipe-stages.