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Hi,
Does anyone know how can I add Hex numbers inside the process (VHDL)?
For instance, I want to add x"55"
+ x"55" but if I'll write " x"55"
or x"55" " the answer will be x"55" (the answer should be x"AA").
Idan
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Of course x"55" or x"55" is x"55" as this is a binary or, used on the vector bitwise.
Addition in VHDL (one of the reasons I prefer Verilog over HDL) requires type conversions as it has quite a strict type checking:
result <= std_logic_vector(unsigned(x"55") + unsigned(x"55"));
Also please note that unless you do know exactly what you do an addition of two vectors with N and M bits require the result to be max(N,M) + 1 bit wide.
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