Honored ContributorPlease help me with calculating timing of the adder. Consider the code
wire dataout = { 1'b0, datain1 } + { 1'b0, datain2 };
Honored ContributorThe way an FPGA works means propagation delays might not be linked directly to this line of code. The compiler/synthesizer might do some optimization. If you use Quartus you can use Timequest. There are some threads about how to use it. I don't know which excactly.
Honored ContributorWell this question is related to TimeQuest and its errors. To be honest I do not understand them, that's why I gather information about how "code" (circuit) works. For some reason TQ says data arrival violation error, which I have problems tracing.
Honored ContributorYou could ask it to give timing closure recommendations. This gives you the path of the signal from source tough to destination. That might help some. It also will tell you stuff like slack etc.
