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Altera_Forum's avatar
Altera_Forum
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11 years ago

Adder timing

Please help me with calculating timing of the adder. Consider the code 

wire  dataout = { 1'b0, datain1 } + { 1'b0, datain2 };

How much time adding will take place (in other words - propagation delay till dataout[17] validity) after one or both data change? Please explain calculation algorithm and give sources of the information. Chip is Cyclone 3 grade 8. Thank you!

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    The way an FPGA works means propagation delays might not be linked directly to this line of code. The compiler/synthesizer might do some optimization. If you use Quartus you can use Timequest. There are some threads about how to use it. I don't know which excactly.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Well this question is related to TimeQuest and its errors. To be honest I do not understand them, that's why I gather information about how "code" (circuit) works. For some reason TQ says data arrival violation error, which I have problems tracing.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    You could ask it to give timing closure recommendations. This gives you the path of the signal from source tough to destination. That might help some. It also will tell you stuff like slack etc.