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Altera_Forum
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10 years ago

Adder timing

Please help me with calculating timing of the adder. Consider the code wire dataout = { 1'b0, datain1 } + { 1'b0, datain2 }; How much time adding will take place (in other words - pro...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

The way an FPGA works means propagation delays might not be linked directly to this line of code. The compiler/synthesizer might do some optimization. If you use Quartus you can use Timequest. There are some threads about how to use it. I don't know which excactly.