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Honored Contributor
Honored ContributorAdder timing
Please help me with calculating timing of the adder. Consider the code wire dataout = { 1'b0, datain1 } + { 1'b0, datain2 }; How much time adding will take place (in other words - pro...
Altera_ForumHonored Contributor
Honored ContributorThe way an FPGA works means propagation delays might not be linked directly to this line of code. The compiler/synthesizer might do some optimization. If you use Quartus you can use Timequest. There are some threads about how to use it. I don't know which excactly.
