ADC0804 interfaced with CPLD

Just for completeness this is the reduce frequency code.

-- Standard libary delarations

library ieee;

use ieee.std_logic_1164.all;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- define input and outputs for the entity

--Entity is the device inputs and outputs

entity adc is port(

--input variable (1-bit)

clk_in: in std_logic;

--buffer can be input or output

clk_out: buffer std_logic;

clk: buffer std_logic);

end adc;

-- internal function of entity

architecture behave of adc is

--internal variable

signal count: integer range 0 to 125000;

begin

process (count, clk_in,clk_out)

begin

--signal clk_out: integer;

-- Required in order to convert the sinewave to a square wave

clk_out <= not clk_in;

-- Check for clock to occur and trigger on rising edge

if(clk_out'event and clk_out='1') then

--increment the count variable by 1

count <=count+1;

if (count = 20) then

clk <= not clk;

-- reset count variable to 1

count <= 1;

-- end all the if statements

end if;

end if;

--end the process

end process;

--end internal function

end behave;

Jag.

Hi Jag,

Reading code is not a very good use of anyone's time when trying to help you.

What you need to do is to supply a testbench that can be run in Modelsim. That allows you to see the waveforms your logic is creating, and it allows the readers of this forum to help you.

I've posted several examples of testbenches before:

http://www.alteraforum.com/forum/showthread.php?t=32386&p=132149#post132149

http://www.alteraforum.com/forum/showthread.php?t=38988&p=160666#post160666

http://www.alteraforum.com/forum/showthread.php?t=35572&p=146930#post146930

Create a testbench for your code and see if it generates the waveforms you expect. Then synthesize the code to see if you get warnings.

If I was going to implement an interface to this ADC, I would create a finite state machine that was clocked by the CPLD clock. That state machine would implement the logic required to read from the device.

For example, Altera's Avalon-MM interface defines a synchronous bus with wait-states and a read-valid output.

But perhaps this is a little advanced at this point.

What is supposed to be reading this ADC?

Cheers,

Dave

Thanks Dave, I will create a testbench as advised. The ADC has a potentiometer as the in

put.

Jag.

--- Quote Start ---

I will create a testbench as advised. The ADC has a potentiometer as the input.

--- Quote End ---

Great.

What I'm trying to do here is advise you on how to approach this problem. If you get stuck, then I'll help out. Take a shot at creating the testbench and getting your code to work, and I'll check it out. If necessary, I'll make some suggestions.

What is the overall plan for this ADC. You have a potentiometer as the input to the ADC, but what does that represent (or what will it represent later on), and who or what will be reading the ADC.

The CPLD board you are using is not very powerful, so you cannot implement a NIOS II processor. Is there a microcontroller on the board that can access the FPGA logic? If so, you could program that microcontroller to access the ADC reading, and then send it to your PC.

Its a good idea to start with a system design, and then start implementing the pieces.

Cheers,

Dave