Honored Contributor
Honored ContributorHi Jag,
Reading code is not a very good use of anyone's time when trying to help you. What you need to do is to supply a testbench that can be run in Modelsim. That allows you to see the waveforms your logic is creating, and it allows the readers of this forum to help you. I've posted several examples of testbenches before: http://www.alteraforum.com/forum/showthread.php?t=32386&p=132149#post132149 http://www.alteraforum.com/forum/showthread.php?t=38988&p=160666#post160666 http://www.alteraforum.com/forum/showthread.php?t=35572&p=146930#post146930 Create a testbench for your code and see if it generates the waveforms you expect. Then synthesize the code to see if you get warnings. If I was going to implement an interface to this ADC, I would create a finite state machine that was clocked by the CPLD clock. That state machine would implement the logic required to read from the device. For example, Altera's Avalon-MM interface defines a synchronous bus with wait-states and a read-valid output. But perhaps this is a little advanced at this point. What is supposed to be reading this ADC? Cheers, Dave
