ADC0804 interfaced with CPLD

Just for completeness this is the reduce frequency code.

-- Standard libary delarations

library ieee;

use ieee.std_logic_1164.all;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- define input and outputs for the entity

--Entity is the device inputs and outputs

entity adc is port(

--input variable (1-bit)

clk_in: in std_logic;

--buffer can be input or output

clk_out: buffer std_logic;

clk: buffer std_logic);

end adc;

-- internal function of entity

architecture behave of adc is

--internal variable

signal count: integer range 0 to 125000;

begin

process (count, clk_in,clk_out)

begin

--signal clk_out: integer;

-- Required in order to convert the sinewave to a square wave

clk_out <= not clk_in;

-- Check for clock to occur and trigger on rising edge

if(clk_out'event and clk_out='1') then

--increment the count variable by 1

count <=count+1;

if (count = 20) then

clk <= not clk;

-- reset count variable to 1

count <= 1;

-- end all the if statements

end if;

end if;

--end the process

end process;

--end internal function

end behave;

Jag.