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Altera_Forum's avatar
Altera_Forum
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14 years ago

ADC output from LVDS deserializer.

Hi,

I have a an ADC sampling at 40 MHz, and it output LVDS signal, so i have to deserialize it using my DE2-115, but i am having trouble with the deserialized signal (shown in the picture), it should display a pure sine wave.

I have no idea what are the possible solution. I am using the lvds_rx block provided from megawizard.

I have not set the .SDC file yet, you think that might solve the problem?

Please comment..

regards,

Michael

33 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    Dynamic phase shift is a basic feature of the PLL blocks since Cyclone III. It can be used to achieve a DPA-like functionality with the LVDS PLL, but not for individual bits. Unlike with hardware DPA, that can be simply enabled in the MegaWizard, you have to design the phase shift state machine and signal edge detector yourself.

    --- Quote End ---

    how hard do you think this can be for a newcomer like me?
  • Altera_Forum's avatar
    Altera_Forum
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    I had a similar ADC only two channels in offset mode 12-bit 80 MSPS. I didn't use the lvds module, but the DDR input megafunctions. The important thing to remember is that this megafunction, which is also in the lvds megafunction, delays your data by one full data clock. This means that if you use both the frame and data clock from your ADC you have to shift your frame clock over by at least one data clock. From here you can do timing reports and continually adjust the frame clock time shift until you get the best results.

    The following SDC worked for me and I've had no timing issues what so ever.

    # # VERITUAL CLOCK FRAME# #
    create_clock -name fpga_clk_frame -period "40MHz" # # VIRTUAL CLOCK DATA# #
    create_clock -name ext_clk1 -period "240MHz"# # INPUT CLOCK WITH 90 DEGREES PHASE SHIFT
    create_clock -name fpga_clk_data -period "240MHz" -waveform {1.042 3.125} 
    set_input_delay -clock ext_clk1 -max 0.250 }]
    set_input_delay -clock ext_clk1 -min -0.250 }]
    set_input_delay -clock ext_clk1 -max 0.250 }] -clock_fall -add_delay
    set_input_delay -clock ext_clk1 -min -0.250 }] -clock_fall -add_delay
    set_input_delay -clock ext_clk1 -max 0.250 }]
    set_input_delay -clock ext_clk1 -min -0.250 }]
    set_input_delay -clock ext_clk1 -max 0.250 }] -clock_fall -add_delay
    set_input_delay -clock ext_clk1 -min -0.250 }] -clock_fall -add_delay
    set_input_delay -clock ext_clk1 -max 0.250 }]
    set_input_delay -clock ext_clk1 -min -0.250 }]
    set_input_delay -clock ext_clk1 -max 0.250 }] -clock_fall -add_delay
    set_input_delay -clock ext_clk1 -min -0.250 }] -clock_fall -add_delay
    set_input_delay -clock ext_clk1 -max 0.250 }]
    set_input_delay -clock ext_clk1 -min -0.250 }]
    set_input_delay -clock ext_clk1 -max 0.250 }] -clock_fall -add_delay
    set_input_delay -clock ext_clk1 -min -0.250 }] -clock_fall -add_delay
    set_false_path -setup -rise_from  -fall_to 
    set_false_path -setup -fall_from  -rise_to 
    set_false_path -hold -rise_from  -rise_to 
    set_false_path -hold -fall_from  -fall_to 
    
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Hi Lewy0701, just wondering if you have succeeded in designing your project? If yes, would you mind sharing with me? Thanks