ADC output from LVDS deserializer.

I had a similar ADC only two channels in offset mode 12-bit 80 MSPS. I didn't use the lvds module, but the DDR input megafunctions. The important thing to remember is that this megafunction, which is also in the lvds megafunction, delays your data by one full data clock. This means that if you use both the frame and data clock from your ADC you have to shift your frame clock over by at least one data clock. From here you can do timing reports and continually adjust the frame clock time shift until you get the best results.

# # VERITUAL CLOCK FRAME# #
create_clock -name fpga_clk_frame -period "40MHz" # # VIRTUAL CLOCK DATA# #
create_clock -name ext_clk1 -period "240MHz"# # INPUT CLOCK WITH 90 DEGREES PHASE SHIFT
create_clock -name fpga_clk_data -period "240MHz" -waveform {1.042 3.125} 
set_input_delay -clock ext_clk1 -max 0.250 }]
set_input_delay -clock ext_clk1 -min -0.250 }]
set_input_delay -clock ext_clk1 -max 0.250 }] -clock_fall -add_delay
set_input_delay -clock ext_clk1 -min -0.250 }] -clock_fall -add_delay
set_input_delay -clock ext_clk1 -max 0.250 }]
set_input_delay -clock ext_clk1 -min -0.250 }]
set_input_delay -clock ext_clk1 -max 0.250 }] -clock_fall -add_delay
set_input_delay -clock ext_clk1 -min -0.250 }] -clock_fall -add_delay
set_input_delay -clock ext_clk1 -max 0.250 }]
set_input_delay -clock ext_clk1 -min -0.250 }]
set_input_delay -clock ext_clk1 -max 0.250 }] -clock_fall -add_delay
set_input_delay -clock ext_clk1 -min -0.250 }] -clock_fall -add_delay
set_input_delay -clock ext_clk1 -max 0.250 }]
set_input_delay -clock ext_clk1 -min -0.250 }]
set_input_delay -clock ext_clk1 -max 0.250 }] -clock_fall -add_delay
set_input_delay -clock ext_clk1 -min -0.250 }] -clock_fall -add_delay
set_false_path -setup -rise_from  -fall_to 
set_false_path -setup -fall_from  -rise_to 
set_false_path -hold -rise_from  -rise_to 
set_false_path -hold -fall_from  -fall_to