Honored ContributorHello,
I have a development board which has SFP+ cages that are hooked up to the xcvr inputs on a Stratix V FPGA development board. I am wondering if I can receive and decode JESD204B signals over this connection. Can Altera's JESD204B ip target the xcvr inputs lanes? If not, can I still write my own and by using transceivers in some custom configuration? Thank you for the insights.
Honored ContributorIdeally there should not be an issue to connect the IP to the XCVR input lanes because the XCVR lanes should be independent from the IP core. The quick way to verify this would be to get the JESD IP and then try to place at the specific lane that you are targeting. Then run through Fitter compilation. Fitter will help to check against placement rules and restrictions. If the IP not allow, you can try the same method with your custom XCVR ie with Custom PHY or Native PHY.
Honored ContributorHi, did you get a solution to your problem? Also, can you run the JESD megafunction without using a NIOS processor?
