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Altera_Forum's avatar
Altera_Forum
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15 years ago

ADC acquisition with FPGA

Hi,

I´m trying to interface an ADC9254 (from ti) converter in VHDL with board DSP Development Board for Stratix II Edition, in order to do an acquisition for signal, but i´m new in this type of design language.

To be clear , the purpose of this project is to locate defects by reflectometry in a wired electric network, so using FPGA i send signal from DAC, after this i should measure the reflected signal and treat it with the ADC.

so i need some help. I´m interested in the vhdl code if it would be possible. Thank you very much.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I can't find this ADC. But looks like you can clock this ADC from PLL in Altera and use other clock (shifted) of this PLL for clock input data.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    i can't use PLL , it's should do another function

    i must use just a dac and adc to measure the reflected signal

    for the dac i generate a pulse wich is the incident signal , now i have to do the acquisition with adc (this one is connected to the dac)

    thank you for your help
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hello,

    there's no ADC9254 from TI. I presume you meant AD9254 from Analog Devices.

    VHDL wise, Interfacing the FPGA with the ADC is, in itself, quite trivial: use the ADC's Data Output Clock to register the ADC's Data Output signals.

    You'll also need to set some ADC parameters. IIRC, most of them can be set through configuration pin. In a worse case scenario, you'll need a small state machine to implement the SPI protocol.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    VHDL wise, Interfacing the FPGA with the ADC is, in itself, quite trivial: use the ADC's Data Output Clock to register the ADC's Data Output signals.

    --- Quote End ---

    And use dedicated clock input pin at same io bank with data bus.