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Altera_Forum's avatar
Altera_Forum
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11 years ago

Active Serial Programming ISSUE EPCS16 EP4CE15

Dear friends,

i have designed and assembled my first fpga board and have some issues with the active serial programming. After programming the config device via usb blaster (which states 100% successful) my fpga remains in unprogrammed state even after reseting. The programming via jtag works without any issues. Because of my lack of experiance with altera cyclone 4 i am not sure if this is a hardware or software issue and appreciate any kind of help.

I will provide some detailed informations below. I am using the Quartus II 14.1 web edition.

1. Settings:

Assignments -> Device - > Device and Pin Options -> Configuration:

Config scheme: active serial (can use config device)

Config mode: standard

use config device: EPSC16

config dev io voltage: auto

force vccio to be compatible: true

generate compressed bitstreams: true

enable input tri-state on active config: false

Programmer:

Mode: active serial programming

Tools -> options:

http://www.alteraforum.com/forum/attachment.php?attachmentid=10829&stc=1

2. pcb schematic for config device

http://www.alteraforum.com/forum/attachment.php?attachmentid=10826&stc=1

3. simple fpga schematics

http://www.alteraforum.com/forum/attachment.php?attachmentid=10827&stc=1

4. POF File

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    After a few hour of programming and debugging i think i have found my bug, i believe my msel config is faulty, because it should have been

    MSEL0 - L

    MSEL1 - H

    MSEL2 - L

    for active serial mode with 3V3, right?

    Is there a possibility to fix this without hardware debugging?
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    You are on to your problem. (Athough I get a different MSEL config for 3.3)

    MSEL 0 = H

    MSEL 1 = L

    MSEL 2 = L

    (for standard AS mode 3.3V)

    MSEL 0 = H

    MSEL 1 = L

    MSEL 2 = H

    (for fast AS mode 3.3 V)

    The mode you have set is Passive Serial mode, so that would require you to provide the clock and control signals.

    (Usually used when a CPU is used to program the FPGA)

    Your only option here is to correct the error unfortunately. Unless your routing is such you can cut a trace and re-wire it for a re-work, it probably means a board spin.

    Pete
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    You are on to your problem. (Athough I get a different MSEL config for 3.3)

    MSEL 0 = H

    MSEL 1 = L

    MSEL 2 = L

    (for standard AS mode 3.3V)

    MSEL 0 = H

    MSEL 1 = L

    MSEL 2 = H

    (for fast AS mode 3.3 V)

    --- Quote End ---

    Hello Pete, i will try to cut/desoder the pin and connect it via a wire to the next vcc via, but i am curious if your or my suggested levels are correct (i do not want to change an error or another). In the cyclone iv device handbook, page 173, table 8.5 is stated

    http://www.alteraforum.com/forum/attachment.php?attachmentid=10833&stc=1

    Could you please confirm this, or am i making a mistake?

    Thank you very much for your help, i appreciate it.

    Best regards

    Nenad
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hello Pete, i will try to cut/desoder the pin and connect it via a wire to the next vcc via, but if am curious if your or my suggested levels are correct (i do not want to change an error or another). In the cyclone iv device handbook, page 173, table 8.5 is stated

    http://www.alteraforum.com/forum/attachment.php?attachmentid=10834&stc=1

    Could you please confirm this, or am i making a mistake?

    Thank you very much for your help, i appreciate it.

    Best regards

    Nenad

    PS: my answeres are getting lost, i hope i have not answered you three times
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hi Need. You are correct.

    I was looking at the table 8-3 (For the GX device).

    Sorry for the confusion.

    Pete
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    nnead, yes set your MSEL pins to L,H,L. You will have to do a hardware change, by physically connecting wires to those nodes (or just cutting the existing MSEL1 track and adding a wire to 3.3V). I recently had to do the same exercise on a BGA b/c i messed up the MSEL pins... not a fun exercise... Hopefully your pcb layout isn't too complicated to debug.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hello Pete,

    thanks again, so now its time for some funny one pin qfp desoldering.

    Best regards

    Nenad
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    nnead, yes set your MSEL pins to L,H,L. You will have to do a hardware change, by physically connecting wires to those nodes (or just cutting the existing MSEL1 track and adding a wire to 3.3V). I recently had to do the same exercise on a BGA b/c i messed up the MSEL pins... not a fun exercise... Hopefully your pcb layout isn't too complicated to debug.

    --- Quote End ---

    Hello krasner,

    thank you for your response. The only solution for me is to desolder one pin, isolate it from its pad (maybe bend over) and solder it via to small wire to some vcc via. Unfortunally i cant cut the track because it is under the fpga. What a pitty, this is my first pcb and i really hoped it would be flawless
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    I know this board is done and over, but what I tend to do, is have these pins either going through 0 ohm resisters to their target voltages, or through surface traces that are exposed outside the perimeter of the FPGA, so that I'm always positive I can fix it with easy rework if I do happen to get it wrong.

    Pete