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Altera_Forum
Honored Contributor
10 years agoYou are on to your problem. (Athough I get a different MSEL config for 3.3)
MSEL 0 = H MSEL 1 = L MSEL 2 = L (for standard AS mode 3.3V) MSEL 0 = H MSEL 1 = L MSEL 2 = H (for fast AS mode 3.3 V) The mode you have set is Passive Serial mode, so that would require you to provide the clock and control signals. (Usually used when a CPU is used to program the FPGA) Your only option here is to correct the error unfortunately. Unless your routing is such you can cut a trace and re-wire it for a re-work, it probably means a board spin. Pete