Active serial configuration

Hi,

Sorry for the late response.

As I mentioned before, in the Stratix 5 user guide, there's no specific JTAG configuration waveform, but only the "CONF_DONE" signal pulling high indicating the completion of the JTAG configuration. But it is true that the nSTATUS signal of the "Faulty Board" looks not normal. So still let's make sure if FPGA is still ok to run.

1. If sof is not configured into the "Faulty board" FPGA, it means that the function of the problem is on FPGA function. This kind of abnormal could be caused by Power. If Power is also ok, then it means FPGA itself is abnormal.
2. If sof is successfully configured into the FPGA, it means FPGA itself is normal. In this case, the problem is either on Board-level connection or FLASH device itself. You may try if the FLASH can work normally to read/write data.

Thanks & Regards,

Xiaoyan