Active serial configuration agilex 5

Hi Dany2,

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For Clock sharing, you may check GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs, 2.6.5. Shared Clocking Resources Between the GTS Transceiver Bank and....

https://www.intel.com/content/www/us/en/docs/programmable/817660/25-1/shared-clocking-resources-between-the.html

You may route the tx_clkout / rx_clkout signals etc from the GTS transceiver IP to core fabric. But as the frequency requirements of different functions you mentioned probably don't match with each other, this may not meet your need.

There's no direct way to feed the clock input from one pair of certain external differential clk pins to both Core fabric and Transceiver.

Best Regards,

Xiaoyan