Achieving Timing Closure on Source Synchronous DDR Input

skew value is up to the vendor to tell you. When they say it is centre aligned DDR then they should indicate their skew. Board itself will also have some skew effect.

If you don't know these figures you can try small value then go up till failure to see your IF tolerance.

PLL is not essential if your adc clock is routed through clock pin. It wouldn't harm anyway so keep it if you wish.

for centre aligned DDR (as well as for edge aligned DDR) there are two patterns of transfer: same edge or opposite edge. This is decided by setting the edge false paths. In your case you are targeting same edge transfer as you are setting false path on rise to fall for setup. If you swap those for hold to those for setup and vice versa then you are targeting opposite edge transfer. In this case your fpga logic should take care of data acquisition order. I believe there are some examples in timequest resource centre.