Achieving Timing Closure on Source Synchronous DDR Input

how do I choose a skew value? should it be on the adc datasheet as I cant see one defined.

Can you elaborate on both ways of edge transfer? I dont understand what you mean.

My only reservation with removing the pll was that the clock input is lvds, can I clock internal logic straight from this? My design registers the ddio output and puts it into a DCFIFO. This means I would have to clock some of the internal logic using the ADC input clock so it was in the correct clock domain. I guess I could drive the DDIO straight from the ADC clock input and also apply this to the pll in source synchronous mode the output of which could drive the internal logic reading the ddio output.

Regards

James