Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

ACEX1k

Hello Guys I am using the ACEX 1k ALTERA with MAXPLUSII In my FPGA I have a 48Mhz clk, in some where I use the 48Mhz clk as input to a "CLKLOCK" block that make from this 48Mhz clk a 96Mhz clk, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

You want to use the 96MHz clock as logic? From what I remember of that family, once you're on a clock tree(which is what the clklock block feeds), there is no way to get off of it. You can go off chip and route back in, or multiply up to 192MHz(if possible) and create a divide by two register.

All new families can get off the clock tree though, if that's an option.