Accessing HPS Pins

I'm not overly familar with the HPS I/O but I suspect because there is no clocking mechanism in the I/O (input/output registers are independent of the HPS I/O except in the case of SDRAM) that it will not be possible to loan those HPS EMAC I/O to the FPGA and be able to implement double data rate interfaces relying on the DDR functionality being included in the I/O itself. My understanding is that HPS I/O loaned out to the FPGA for the most part is pin <--> I/O buffer <--> muxes <--> FPGA fabric. I suspect the double data rate that is implemented for the HPS EMACs is independent of the I/O themselves and as a result FPGA logic borrowing those same I/O will not inherit that functionality. In other words the path between the HPS EMAC and the HPS I/O would be pin <--> I/O buffer <--> muxes <--> registers (where I suspect DDR is implemented) <--> EMAC

If you need that functionality and have not done so I recommend opening a service request so that someone can take a closer look at this. If it's really just a tools issue then that most likely can be resolved but I suspect it's a limitation of the implementation.