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This is not actually a tool issue, the I/O used by the HPS are physically different than the ones on the FPGA side of the Cyclone/Arria V SoC device.
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I see your point about the I/O not being general-purpose FPGA I/O. But given that the I/O that I am loaning to the fabric are in fact used to implement an RGMII to the HPS MAC, then it's clear that the I/O themselves are capable of implementing a DDR function, and I don't see why I shouldn't be able to, via some constraint magic, be able to configure them and use them as such from the FPGA fabric. This is what I mean by a "tool issue"; the silicon is clearly capable of implementing the function that I need.