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Altera_Forum's avatar
Altera_Forum
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12 years ago

About the max DDR3 rate

Hi,

I need to use ddr3 at 800Mbps,Due to the cost reason,I am planning to use cyclone V .

I want to know,can users implement the ddr3 interface working at the maximum data rate giving in datasheet long term when using the DDR3 controller ip?

or users must to use the DDR3 controller at lower data rate than the maximum rate giving in datasheet?

Thanks.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Refer to the external memory performance (http://www.altera.co.uk/literature/hb/cyclone-v/cv_52006.pdf) Datasheet, page 2. The hard controllers can operate up to 400MHz. You can rely on these working at that frequency for the expected life of the FPGA.

    This also states the maximum frequency of an FPGA operating a soft core memory controller. This is the maximum possible but will be dependant upon you particular design. Quartus will report the max frequency of your design. You can rely on your design operating at that frequency for the life of the FPGA.

    Regards,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    Refer to the external memory performance (http://www.altera.co.uk/literature/hb/cyclone-v/cv_52006.pdf) Datasheet, page 2. The hard controllers can operate up to 400MHz. You can rely on these working at that frequency for the expected life of the FPGA.

    This also states the maximum frequency of an FPGA operating a soft core memory controller. This is the maximum possible but will be dependant upon you particular design. Quartus will report the max frequency of your design. You can rely on your design operating at that frequency for the life of the FPGA.

    Regards,

    Alex

    --- Quote End ---

    Thank you very much.