The Stratix4 handbook said the setup time of input pin is about 200ps. Does it means a signal about 3Gbps could pass through the IO pins in Stratix4 devices, and I can use plural clocks(300MHz) with different phase to over-sample the signal?

Is the hold time 0ns? I'm guessing not. I don't know why they even give setup/hold times anymore, since PLLs/delay chains allow you to shift to about any setup time you want(but always at the expense of hold). For 3Gbps, you would need to use the high-speed transceivers. For 1.6Gbps down to approximately 900Mbps, you can use LVDS with DPA. For 900Mbps downto 500MBps, straight LVDS should work. For below 500Mbps, regular I/O using DDR registers should work. Those are really rough figures off the top-of-my-head, and dependent on I/O standard, board layout, speed grade, the other device being connected to, etc., but hopefully in the right ballpark.

--- Quote Start --- Is the hold time 0ns? I'm guessing not. I don't know why they even give setup/hold times anymore, since PLLs/delay chains allow you to shift to about any setup time you want(but always at the expense of hold). For 3Gbps, you would need to use the high-speed transceivers. For 1.6Gbps down to approximately 900Mbps, you can use LVDS with DPA. For 900Mbps downto 500MBps, straight LVDS should work. For below 500Mbps, regular I/O using DDR registers should work. Those are really rough figures off the top-of-my-head, and dependent on I/O standard, board layout, speed grade, the other device being connected to, etc., but hopefully in the right ballpark. --- Quote End --- Thanks for your answer. I'm trying to build a high speed data acquisition equipment using Stratix4. As you said, transceivers must be in use for 3Gbps. But the transceivers cannot work without a CDR(though the input data is random), in other words, they may not work in my design. So, i'm helpless. I want to sample the high speed data, but have no idea to acquired. The method of using FISO(Fast In Slow Out) chip will be helpful, but those chips always be used by companys like Agilent, Tek as ASIC. Seems no general FISO IC in market.

I don't think regular I/O are the way to go. 3Gbps just seems way too out there. Could you use a transceiver and just hold the CDR unit in "lock to ref" mode instead of lock to data? That way you're not really recovering a clock out of it? (I may be way off base, just throwing out an idea...)

--- Quote Start --- Could you use a transceiver and just hold the CDR unit in "lock to ref" mode instead of lock to data? That way you're not really recovering a clock out of it? (I may be way off base, just throwing out an idea...) --- Quote End --- Ryan is correct, you can do this. Its can be used to create a 1-bit high-speed ADC. You configure the XCVR in basic mode and implement manual control of the CDR lock-to-reference and lock-to-data control signal. Its not that great for creating a multi-channel ADC, since each receiver deserializer starts independently. What types of signals are you planning on sampling? If you want to oversample, then you gain 1-bit (6dB ) for every 4x oversampling. How many bits (what dynamic range) do you need in your final signal? I don't think you can implement a sigma-delta converter, since you need to convert the signal back to analog, and there is an unknown delay in the receiver-back-to-transmitter path. You can do this with LVDS buffers. I think Altera has a MAX II app note that shows sigma-delta, and Lattice definitely has one. Cheers, Dave

--- Quote Start --- I don't think regular I/O are the way to go. 3Gbps just seems way too out there. Could you use a transceiver and just hold the CDR unit in "lock to ref" mode instead of lock to data? That way you're not really recovering a clock out of it? (I may be way off base, just throwing out an idea...) --- Quote End --- Hello Rysc!! i'm so glad to receive your answer above, because I had tried to use a transceiver,and lock its clock to ref clk. That method worked, but one deserialized channel cannot be sync well. For example, the deserializer factor is 10, all the deserialize channels synchronized to the slow clock, except the channel 5. The data on ch5 was asserted after the slow clock's rising edge(Tsu is negtive), the data on other channels was valid before the rising edge.

About Stratix4 IO feature | Altera Community

12 Replies

Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
Right, but there is a slight difference in what happens if you sample directly with the FPGA receiver. In that case, the input analog signal is encoded as a 0 or 1 based on the analog input voltage at the time the receiver samples the input. By putting a digital comparator in front of the receiver, you are changing the signal seen by the receiver to a binary signal with fast edge transitions. These edge transitions are not synchronous to the receiver clock, so when it samples, it can still produce a metastable output value.

Its not clear to me that there is any advantage in adding the comparator, unless of course it was clocked synchronously with the receiver. You might be better off with a limiting amplifier or clamping diodes on the input, so as not to violate the receiver voltage limits.

You must be recovering some information from the input, otherwise you would not sample it! So what information are you interested in? The power spectrum?

Cheers,
Dave
--- Quote End ---

I'm sorry, I didn't explain my design clearly.
In shrot, it works like a logic analyzer very much, a logic analyzer work in timing analyzing mode.
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---

In shrot, it works like a logic analyzer very much, a logic analyzer work in timing analyzing mode.
--- Quote End ---

ByteParadigm have a device that does this using a Xilinx part:

http://www.byteparadigm.com/files/documents/thunderseries_wp.pdf

Cheers,
Dave

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About Stratix4 IO feature

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