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Right, but there is a slight difference in what happens if you sample
directly with the FPGA receiver. In that case, the input analog signal is encoded as a 0 or 1 based on the analog input voltage at the time the receiver samples the input. By putting a digital comparator in front of the receiver, you are changing the signal seen by the receiver to a binary signal with fast edge transitions. These edge transitions are not synchronous to the receiver clock, so when it samples, it can still produce a metastable output value.
Its not clear to me that there is any advantage in adding the comparator, unless of course it was clocked synchronously with the receiver. You might be better off with a limiting amplifier or clamping diodes on the input, so as not to violate the receiver voltage limits.
You must be recovering some information from the input, otherwise you would not sample it! So what information are you interested in? The power spectrum?
Cheers,
Dave
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I'm sorry, I didn't explain my design clearly.
In shrot, it works like a logic analyzer very much, a logic analyzer work in timing analyzing mode.
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