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Altera_Forum
Honored Contributor
Honored Contributorabout if
hello,
do you know how to terminate an "if" instruction? the instructions are repeating over and over again and i don't want to repeat.I need a break terminal or something like that.I search on the net but it doesn't work.If you know...please help. Best regards, tastax4 Replies
Altera_Forumthx a lot! your example was very helpfull for me and it works for my project!
- Altera_Forum
It will be executed every time the clock comes.
The only way to avoid it is to remember that it was already ran once: logic once = 1'b0; always @ (posedge clk) begin if (once == 1'b0) begin // insert your code here once <= 1'b1; // remember that it already ran once end end - Altera_Forum
is in verilog and is in a clocked always block. How can i execute the if instruction just once?
- Altera_Forum
if in C on a Nios ?
if in VHDL ? if in Verilog ? Is the "if" in HDL and is it inside a clocked process/always block ?
