About cyclone II diferential LVDS pins

As odd and crazy as it looks, this should work just as poorly as the Xilinx example in the referenced link.

Go for it and post your results here.

I do not think that you can use 1 input pair to get 25 steps, it will take many input pairs unless I am missing something. In the reference example, he is using 16 input pairs (IBUFDS_LVDSEXT_25)

Good luck,

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I do not think that you can use 1 input pair to get 25 steps, it will take many input pairs unless I am missing something.

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That example in link use ADC conversion Flash ADC type technique -> one comparator for each bite, but I plan to use same technique like SAR adc converters they have ONE comparator + one DAC and they are sersching analog signal by steps changing one of comparator inputs by DAC, I already created sutch type ADC using AVR atmega8 (500Ksps) but problem was that this serching algoritm tooks all mega8 instruction so when I add aditional code ADC speed decreases to 75Ksps (it is too slow)

I think that fpga could be solution (I already wrought some VHDL code but didn't tested jet coud has State machine (8 states) and consumes just 40Le and max clock speed is about 250Mhz :) so abvios that fpgas can outperform atmega8 more that 130X

I hope tomorow I will put 2.5V VCCIO and test this chanel (I will put some Osciloscope pictures too

I think I burned my EP2C8 208 :( past 2 days I was making this 2.5V VCCIO and problem was with my self soldered byteblaster II (LTP port) it just didn't worked on these 2.5V so it took me 2 days of soldering (I added adition 74hc244 buffer for 2 output lines and put additional 5V power supply to byteblaster to make 5V signal out of 2.5V signal that was going to parallel port and when BBII was working I add this test circuit and something happened :confused:

my oscillator showed 4,5V on VCCIO instead of 2.5V supply so now it is something wrong with L5973d DC-dc converter it now makes 4,5V (also all my led test diodes burn out (too high voltage :( ) I adjusted L5973d regulator to 1,2V and gived out 0.8V so abviously there is somthing wrong with it but now fpga was not heating up,

also Core voltage VCCINT powers suply brake down and was makng 2.4V (insted of 1.2V) but I found problem and now it gives 1.2V so I have only one DC regulator broken.

I don't know what really happened maybe it was static discharge that brake all.

luckily I have second fpga board wich I also switched to 2.6V and I hope it will work.

Can cyclone II survive VCCINT 2.4V and VCCIO 4.5-5V ???

finally It Works I tested LVDS and they realy was triggering with 100mv difference. Here is oscilloscope picture

so was using resistor divider to supply LVDS negative pin it was 1.36V and then by changing positive pin with potentiometer (blue line in picture is LVDS positive input) and I connected LVDS pin Output to simple IO and red shows LVDS pin logic states. I think this LVDS pin is triggering very fast my oscilloscope has just 1msps.

https://www.alteraforum.com/forum/attachment.php?attachmentid=114

here is my second fpga board (this my self made board that I was developing). In nios forum there is a topic how I made it :)

https://www.alteraforum.com/forum/attachment.php?attachmentid=115

Good and Bad.

I think that you may have killed the chip.

Vccint should not tolerate the 2.4 volts and I/O should not tolerate the 4.5 volts.

Ouch.

Nice job on the rest fo the effort.

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here is picture of first searching algorithm.(it is realy simple:

Process(clock)
begin
if rising_edge(clock) then
	if reset ='1' then DAC_reg <= "01000"; S_loop <= starts;
	else S_loop <= starts;
		case S_loop is 
			when Starts => if COMP ='0' then S_loop <= Minus;
				else S_loop <= Plus; end if;
			when Plus => if (DAC_reg = ALL_ones) then  S_loop <= Starts ; 
						else DAC_reg <= DAC_reg + 1;  S_Loop <= Starts;
					end if;
	
			when Minus => 
				if DAC_reg ="00000" then  S_loop <= Starts ; 
					else DAC_reg <= DAC_reg - 1;  S_Loop <= Starts;
				end if;
				when Others => S_loop <= Starts;
		End case;
	end if;
end if;
end process;

(I used state machine + aditional code to not owecome DAC max, min values like 00000, 11111)

blue line is analog signal and red line is DAC converter output that is connected to LVDS pins negative side and positive pins input is analog signal(blue line).

https://www.alteraforum.com/forum/attachment.php?attachmentid=116

as you can see it is possible to make adc out of fpga's LVDS pins but this resolution is pour but I have idea how to make this resolution higher and how to get more accurate results using more complex searching algorithm.

To day I tested LVPECL differential clock pin and they worked too. actually these lvpecl pins are better suited for such ADC converter because their working range is higher till 3.3V with same 100mv threshold level so I got extra 8 adc levels by 100mv steps :).

bad thing is that my Ep2C8 have just 4 differential LVpecl comparators :( and one pin is using 16Mhz clock so I have just 3 usable LVPECL pins for ADC conversion I also checked other cyclone series fpgas and they all have these LVPECL pins just at clock pins so their count is very small :(