About cyclone II diferential LVDS pins

here is picture of first searching algorithm.(it is realy simple:

Process(clock)
begin
if rising_edge(clock) then
	if reset ='1' then DAC_reg <= "01000"; S_loop <= starts;
	else S_loop <= starts;
		case S_loop is 
			when Starts => if COMP ='0' then S_loop <= Minus;
				else S_loop <= Plus; end if;
			when Plus => if (DAC_reg = ALL_ones) then  S_loop <= Starts ; 
						else DAC_reg <= DAC_reg + 1;  S_Loop <= Starts;
					end if;
	
			when Minus => 
				if DAC_reg ="00000" then  S_loop <= Starts ; 
					else DAC_reg <= DAC_reg - 1;  S_Loop <= Starts;
				end if;
				when Others => S_loop <= Starts;
		End case;
	end if;
end if;
end process;

(I used state machine + aditional code to not owecome DAC max, min values like 00000, 11111)

blue line is analog signal and red line is DAC converter output that is connected to LVDS pins negative side and positive pins input is analog signal(blue line).

https://www.alteraforum.com/forum/attachment.php?attachmentid=116

as you can see it is possible to make adc out of fpga's LVDS pins but this resolution is pour but I have idea how to make this resolution higher and how to get more accurate results using more complex searching algorithm.