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Matt1's avatar
Matt1
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

A10 SoC: issue with .sopcinfo file while generating dts file

During the system design using platform designer, the FPGA EMIF (port: ctrl_amm_0) is interfaced to the HPS system h2f_axi_master and an sopcinfo info file was generated.

when i try to execute the sopc2dts command i am getting the following comment.

"component fpga_emif1 of class alter_emif is unknown"

I am afraid why alter_emif is not identified while creating the sopcinfo file as alter_emif is the IP from IP catalog.

Can somebody help me to circumvent this issue?

thanks and regards

Matt

5 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    Are you trying to use the hard memory controller dedicated to the HPS or connecting the H2F bridge to a separate memory controller through the FPGA fabric? If it's the dedicated controller, you need to enable its use in the HPS parameters and connect the conduit interface that gets enabled to a special IP for this purpose (Arria 10 External Memory Interface for HPS).

    If indeed you are going through the fabric, altera_emif is the correct IP to use. Does the system generate successfully from Platform Designer before you run sopc2dts?

    #iwork4intel

    • Matt1's avatar
      Matt1
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      i am trying to connect the memory controller ,"External Memory Interface intel Arria 10 FPGA IP" to the HPS h2f_axi_master bus.

      Yes,the Generation was done successfully and even i could find the component declaration in the sopcinfo file as

      " <module name="fpga_emif1" kind="altera_emif" version="18.0" path="fpga_emif1">"

  • FawazJ_Altera's avatar
    FawazJ_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    5 years ago

    Hello,

    Can you send me the .qsys file for investigation?

    Which Quartus version are you using?

    Thank you

    • Matt1's avatar
      Matt1
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      sure...i am using Quartus prime 18.0,

      regarding the attached sources...

      In the design i have added PCIe HIP too,..I am concerned only about the altera_emif as it is not recognized while running sopc2dts command in soc eds command shell.

      In the *.dts file i could see the following script for altera_emif.

      fpga_emif: unknown@0x000000000 {

      compatible = "unknown,unknown-18.0";

      reg = <0x00000000 0x00000000 0x10000000>;

      }; //end unknown@0x000000000 (fpga_emif)

      The background is , i want the HPS to communicate to the altera_emif so i connected the h2f_axi_master port of HPS to the ctrl_amm_0 port of EMIF.

      • Matt1's avatar
        Matt1
        Icon for Occasional Contributor rankOccasional Contributor
        5 years ago

        Hi FJumaah,

        any updates regarding the above case!!

        I am a bit confused after reading the below info!!

        i got an info from intel website with the title "Spurious Error Messages from sopc2dts" and its is with reference to Arria V and cyclone V devices.

        Description:

        When you are generating the device-tree source file (.dts) for an SoC HPS hardware design, you might see a large number of spurious error messages. The following list shows some of messages produced by sopc2dts:

        sopc2dts --input soc_system.sopcinfo --output soc_system.dts --board

        soc_system_board_info.xml

        Failed to find h2f_lw_reset

        Failed to find f2h_reset

        Component hps_0 of class altera_hps is unknown

        Workaround/Fix:

        No workaround is necessary. You can safely disregard the warning messages and proceed to compile your device tree sources normally.

        why it so?is it valid for A10 soc?

        Source:

        https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/fb127751.html

        regards

        matt