Occasional Contributor
Occasional Contributorsure...i am using Quartus prime 18.0,
regarding the attached sources...
In the design i have added PCIe HIP too,..I am concerned only about the altera_emif as it is not recognized while running sopc2dts command in soc eds command shell.
In the *.dts file i could see the following script for altera_emif.
fpga_emif: unknown@0x000000000 {
compatible = "unknown,unknown-18.0";
reg = <0x00000000 0x00000000 0x10000000>;
}; //end unknown@0x000000000 (fpga_emif)
The background is , i want the HPS to communicate to the altera_emif so i connected the h2f_axi_master port of HPS to the ctrl_amm_0 port of EMIF.
Occasional ContributorHi FJumaah,
any updates regarding the above case!!
I am a bit confused after reading the below info!!
i got an info from intel website with the title "Spurious Error Messages from sopc2dts" and its is with reference to Arria V and cyclone V devices.
Description:
When you are generating the device-tree source file (.dts) for an SoC HPS hardware design, you might see a large number of spurious error messages. The following list shows some of messages produced by sopc2dts:
sopc2dts --input soc_system.sopcinfo --output soc_system.dts --board
soc_system_board_info.xml
Failed to find h2f_lw_reset
Failed to find f2h_reset
Component hps_0 of class altera_hps is unknown
Workaround/Fix:
No workaround is necessary. You can safely disregard the warning messages and proceed to compile your device tree sources normally.
why it so?is it valid for A10 soc?
Source:
https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/fb127751.html
regards
matt
