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Matt1's avatar
Matt1
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

A10 SoC: issue with .sopcinfo file while generating dts file

During the system design using platform designer, the FPGA EMIF (port: ctrl_amm_0) is interfaced to the HPS system h2f_axi_master and an sopcinfo info file was generated. when i try to execute the s...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
5 years ago

Are you trying to use the hard memory controller dedicated to the HPS or connecting the H2F bridge to a separate memory controller through the FPGA fabric? If it's the dedicated controller, you need to enable its use in the HPS parameters and connect the conduit interface that gets enabled to a special IP for this purpose (Arria 10 External Memory Interface for HPS).

If indeed you are going through the fabric, altera_emif is the correct IP to use. Does the system generate successfully from Platform Designer before you run sopc2dts?

#iwork4intel

  • Matt1's avatar
    Matt1
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    i am trying to connect the memory controller ,"External Memory Interface intel Arria 10 FPGA IP" to the HPS h2f_axi_master bus.

    Yes,the Generation was done successfully and even i could find the component declaration in the sopcinfo file as

    " <module name="fpga_emif1" kind="altera_emif" version="18.0" path="fpga_emif1">"