A trouble With Code

Hi all,

well am a new VHDL programmer, and I was trying to write a code for a generic multiplier using a 4 bit ripple adder, the results are correct, but my design should include two modes, test mode and normal mode, when I was trying to compile the following code, an error occured as follows.

Error (10028): Can't resolve multiple constant drivers for net "output[10]" at fast_multiplier.vhd(19)

here is the code

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY fast_multiplier IS

GENERIC (n: POSITIVE:=7);

PORT(mode,TDI,clk_normal,clk_test:IN STD_LOGIC;

multiplier: IN STD_LOGIC_VECTOR(n-1 DOWNTO 0);

multiplicand: IN STD_LOGIC_VECTOR(3 DOWNTO 0);

result: OUT STD_LOGIC_VECTOR(n+3 DOWNTO 0);

TDO: OUT STD_LOGIC);

END ENTITY;

ARCHITECTURE simple OF fast_multiplier IS

SIGNAL input1: STD_LOGIC_VECTOR(n-1 DOWNTO 0);

SIGNAL input2: STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL output: STD_LOGIC_VECTOR(n+3 DOWNTO 0);

SIGNAL clk: STD_LOGIC;

BEGIN

g0: ENTITY WORK.multiplier_ripple(simple) GENERIC MAP(7) PORT MAP(input1,input2,output);

g1: ENTITY WORK.my_mux(simple) PORT MAP(clk_normal,clk_test,mode,clk);

PROCESS(mode,clk)

BEGIN

IF RISING_EDGE(clk) THEN

IF mode='0' THEN

input1<=multiplier;

input2<=multiplicand;

result<=output;

ELSIF Mode='1' THEN

input2(3 DOWNTO 0)<= (TDI & input2(3 DOWNTO 1)) ;

input1(n-1 DOWNTO 0)<= input2(0) & input1(n-1 DOWNTO 1);

output(n+3 DOWNTO 0)<= input1(0) & output(n+2 DOWNTO 0);

TDO<=output(n+3);

END IF;

END IF;

END PROCESS;

END ARCHITECTURE;

when mode=0 this is the normal mode

and when mode=1 this is the test mode

any help plz as soon as possible