a question about verilog hdl?

What is a? Which differences do you expect? I expect no differences, cause both expressions are functionally identical by Verilog specification, either for a bit or a vector.

Discussing possible synthesis results is meaningless without considering the following action, I think. If you set e.g. two registers depending on the comparison result, not all bits of a (assuming it's a vector) may be evaluated by identical LUTs due to optimisation.