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Altera_Forum
Honored Contributor
16 years agoYou'll find all the documents you need here (http://www.altera.com/products/devkits/altera/kit-nios-2c35.html).
From what I see no the schematic, you have a single 50MHz clock source that is connected to the FPGA on pins P25 (osc_CLK0), AC13 (osc_CLK1), N2 (SRAM_CLKIN) and B13 (SDRAM_CLKIN)