A Quartus13.1 bug - RTL Viewer

Dear all, my english is bad.

Today,I write a simple Verilog code, as follow:

****************************************************

module Linear2addr( X_addr_in,

Sram_addr);

input[9:0] X_addr_in;

output[19:0] Sram_addr;

assign Sram_addr = X_addr_in * 10'd800;

endmodule

****************************************************

It's only a 10bit input multiply a constant value 10'd800, All is simple,but after complete compilation, click RTL viewer -> RTL viewer , I find something is wrong:

https://www.alteraforum.com/forum/attachment.php?attachmentid=8784

You can see 10'h13 in picture above , but i specify in Verilog code is 10'd800 (HEX format is 10'h320),Why in RTL viewer is 10'h13?

I aslo copy the code to synplify pro , then see the rtl , all is right.