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Altera_Forum's avatar
Altera_Forum
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17 years ago

a basic timer in VHDL

hi, how can I write a program for a timer which counts up to 6.4 micro seconds? thanks in advance
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago


entity timer is
end entity timer;
architecture time of timer is
  signal timer : std_logic;
begin
  
  timer <= '0', '1' after 6.4 us;
end architecture time;