Altera_Forum
Honored Contributor
18 years ago93% usage, ripple clocks warning
The outputs are doing what I want them to, but I'm getting warnings about ripple clocks, etc.
The compiler says 93% usage (60/64 cells). Would like to stick with the lower cost 44 pin device. Warnings come from an edge detector used to create a trigger pulse. The registered "signal" clocks a DFF (D=1), Q loads a counter, then overflow resets the DFF. Q is the resulting trigger pulse. For the counter, I used a 74161. I added two cascaded TFF's to give me a total pulse width of 64 clocks. I searched and saw a post about using FF enables to do this, but don't understand. This is for an engine timing controller. Eight inputs, eight outputs, plus a couple of signals to and from a uP. One degree of timing at 10,000 RPM is 16.6 usec. Don't see a need for a clock faster than 1Mhz. Can I ignore the warnings, or do I need to go to the next bigger device and fix it?