72-bit version of LPM_DIVIDE

try using the numeric_std package to do this:

signal a : unsigned(71 downto 0);
signal b : unsigned(71 downto 0);
signal c : unsigned(15 downto 0);
..
a <= b/c;

Thanks. I know this one. I forgot to mention that it cannot be pipelined version, and if so, then the latency must be known so I could resynchronize the data. (of course we are talking about synthesizable design)

Then remove the pipelining registers and do the above code.

If you don't care about latency you could implement this to be very small and fast through serial division. If the latency is too high then you can shift to a partial parallel division implementation which will be larger and slower in terms of fmax. Both are based on long division (you know that stuff you learned in school and never thought you would ever have to use it later in life :))

Besides the interesting discussion about register retiming, it should be mentioned, that infered lpm_divide Megafunctions are limited to 64 bit width as well.

Dear all,

If you want an example of a fully serial divider let me know and I can look around for the verilog prototype I made that I shifted over into C code for C2H.

That's ok. thanks. I'll just modify one I already did before.