Forum Discussion
Altera_Forum
Honored Contributor
16 years agoDear all,
thanks for fruitful hints. I decided to go for fully serial divider. I've found that the 64bit single clock works for 8MHz only (1s20 device), as i need at least 40MHz there is definitely no way how to achieve it using single clock cycle algo. This means to refurbish part of the design to queue the data stream d.